(1) Field of the Invention
The present invention relates to a semiconductor integrated circuit device (Large-Scale Integration (LSI)), and more particularly relates to a semiconductor integrated circuit device for preventing or suppressing a change in electrical performance of a device, such as a transistor, resulting from stress caused by the isolation region to active region of the device.
(2) Description of Related Art
A known semiconductor integrated circuit device will be described with reference to FIG. 12 (for example, see Japanese Unexamined Patent Publication No. 2001-332706).
As shown in FIGS. 12A and 12B, in a dynamic random access memory (DRAM) device formed on a semiconductor substrate 200 made of silicon, p-channel and n-channel transistor regions 211 and 212 forming a sense amplifier are placed apart from each other between a memory cell array 210 and a peripheral circuit 213. Further, a plurality of stress interference blocking patterns 215 for preventing stress interference are formed between the memory cell array 210 and the p-channel transistor region 211, between the p-channel transistor region 211 and the n-channel transistor region 212, and between the n-channel transistor region 212 and the peripheral circuit 213, respectively. Each stress interference blocking pattern 215 is interposed between each two of isolation (Shallow Trench Isolation: STI) regions 201 extending parallel to each other.
The stress interference blocking patterns 215, which form dummy active regions, reduce a difference in stress resulting from the isolation region 201, for example, between the active regions of the p-channel and n-channel transistor regions 211 and 212. This can suppress deterioration in sensitivity of the sense amplifier caused by the difference in threshold voltage (Vth) between the p-channel and n-channel transistors.
However, the known semiconductor integrated circuit device is merely for reducing stress interference in a particular element pattern limited to the active regions of differentially operating transistors such as p-channel and n-channel transistors.
In recent years, semiconductor integrated circuit devices are becoming finer so that their structures are becoming more complicated. Under these circumstances, a difference in stress is produced between the end of an active region forming a device such as a transistor and the central part of the active region. Thus, a change in transistor electrical performance resulting from this stress difference is becoming unignorable. Changes in transistor electrical performance due to stress include, for example, fluctuations in threshold voltage and driving current. Such changes in characteristics increase 1/f noise in an integrated circuit or often induce the phenomenon that the margin of the driving timing decreases.